The present invention generally relates to memory devices for use with computers, including personal computers, workstations and other processing apparatuses. More particularly, this invention relates to high speed nonvolatile or permanent memory-based mass storage devices whose performance can be enhanced by providing banks of nonvolatile memory devices and independent memory controllers, wherein each controller is operable to access each bank via a crossbar switch. The controllers are functionally completely independent of each other, allowing concurrent read and write accesses to the nonvolatile memory devices.
Mass storage devices, such as advanced technology (ATA) or small computer system interface (SCSI) drives, are rapidly adopting nonvolatile (or permanent) memory technology, such as flash memory or other emerging solidstate memory technology (commonly referred to as solid-state drives, or SSDs), including but not limited to phase change memory (PCM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), ferromagnetic random access memory (FRAM), organic memories, or nanotechnology-based storage media such as carbon nanofiber/ nanotube-based substrates. Currently the most common technology uses NAND flash memory as inexpensive storage memory.
The performance of current SSDs is limited by several factors. In sequential transfers, that is, either reads or writes of contiguous blocks of data, the host transfer rate sets an effective limitation for the achievable data exchange between the device and the host. The transfer of data between the drive's controller on the device side and the host bus adapter (in most cases a SATA controller) on the motherboard is currently limited to 3.0 Gbit/sec, which translates into a roughly 280 MB/sec (including protocol overhead) real-world transfer limitation.
Sequential transfers of large data blocks are important for certain classes of applications, a notable but nonlimiting example of which is editing of audiovisual content streams. However, especially in the case of system drives, that is, drives that contain the operating system (OS), house-keeping data are frequently written back to the drive. In most cases those data blocks are in the order of about 4 to about 32 kilobytes (kB). Moreover, the access of these data in both read and write scenarios is highly random.
Particularly in the case of NAND flash memory, any random access incurs an initial latency of the flash memory device on the order of approximately 50 to 100 microseconds. Some of these latencies can be hidden by temporarily storing small data blocks in the drive's cache and then combining them to larger chunks of data to increase the write efficiency and decrease what is known as write magnification. Write magnification means the amount of data written by the controller to the memory devices divided by the data transferred from the host to the device. Since every write access incurs a minimum amount of a page of NAND flash memory being written, write combining is an efficient and necessary protocol to reduce the write amplification factor by combining small data fragments to match the page size within a NAND flash memory array.
In the case of mixed read-write workloads of small data, the overall transfer rates become limited by switching latencies of the controller and, moreover, initial access latencies of the NAND flash memory. This effectively limits the performance of system drives.